Equivalence Checking for High - Level Synthesis Flow

An abstract of the thesis of Yan Chen for the Master of Science in Computer Science presented July 8, 2008. Title: Equivalence Checking for High-Level Synthesis Flow High-level synthesis provides a promising solution to design complicated circuits, but the lack of designers’ confidence in correctness of synthesis tools prevents the wide acceptance in engineering practice. I develop an equivalence checking algorithm within a framework for certifying high-level synthesis flow. I utilize a new formal structure clocked control data flow graph (CCDFG) to facilitate the equivalence checking process, and implement the prototype tool for verifying the equivalence between CCDFG and synthesized circuit in both bit-level and word-level. Experimental results demonstrate the effectiveness of the tools in quickly verifying, or finding bugs in the high-level synthesis flow. EQUIVALENCE CHECKING FOR HIGH-LEVEL SYNTHESIS FLOW